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DM74LS373 * DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops
April 1986 Revised November 2001
DM74LS373 * DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops
General Description
These 8-bit registers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the DM74LS373 are transparent Dtype latches meaning that while the enable (G) is HIGH the Q outputs will follow the data (D) inputs. When the enable is taken LOW the output will be latched at the level of the data that was set up. The eight flip-flops of the DM74LS374 are edge-triggered D-type flip flops. On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D inputs. A buffered output control input can be used to place the eight outputs in either a normal logic state (HIGH or LOW logic levels) or a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus lines significantly. The output control does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered even while the outputs are OFF.
Features
s Choice of 8 latches or 8 D-type flip-flops in a single package s 3-STATE bus-driving outputs s Full parallel-access for loading s Buffered control inputs s P-N-P inputs reduce D-C loading on data lines
Ordering Code:
Order Number DM74LS373WM DM74LS373SJ DM74LS373N DM74LS374WM DM74LS374SJ DM74LS374N Package Number M20B M20D N20A M20B M20D N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
(c) 2001 Fairchild Semiconductor Corporation
DS006431
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DM74LS373 * DM74LS374
Connection Diagrams
DM74LS373 DM74LS374
Function Tables
DM74LS373 Output Control L L L H Enable G H H L X D H L X X Output H L Q0 Z Output Control L L L H DM74LS374 Clock D H L X X Output H L Q0 Z

L X
H = HIGH Level (Steady State) L = LOW Level (Steady State) X = Don't Care Z = High Impedance State = Transition from LOW-to-HIGH level Q0 = The level of the output before steady-state input conditions were established.
Logic Diagrams
DM74LS373 Transparent Latches DM74LS374 Positive-Edge-Triggered Flip-Flops
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2
DM74LS373 * DM74LS374
Absolute Maximum Ratings(Note 1)
Supply Voltage Input Voltage Storage Temperature Range Operating Free Air Temperature Range 7V 7V
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation.
-65C to +150C
0C to +70C
DM74LS373 Recommended Operating Conditions
Symbol VCC VIH VIL IOH IOL tW tSU tH TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Pulse Width (Note 3) Enable HIGH Enable LOW 15 15 5 20 0 70 Parameter Min 4.75 2 0.8 Nom 5 Max 5.25 Units V V V mA mA ns ns ns
-2.6
24
Data Setup Time (Note 2) (Note 3) Data Hold Time (Note 2) (Note 3) Free Air Operating Temperature
C
Note 2: The symbol () indicates the falling edge of the clock pulse is used for reference. Note 3: TA = 25C and VCC = 5V.
DM74LS373 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II IIH IIL IOZH IOZL IOS ICC Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Off-State Output Current with HIGH Level Output Voltage Applied Off-State Output Current with LOW Level Output Voltage Applied Short Circuit Output Current Supply Current Conditions VCC = Min, II = -18 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIL = Max, VIH = Min IOL = 12 mA, VCC = Min VCC = Max, VI = 7V VCC = Max, VI = 2.7V VCC = Max, VI = 0.4V VCC = Max, VO = 2.7V VIH = Min, VIL = Max VCC = Max, VO = 0.4V VIH = Min, VIL = Max VCC = Max (Note 5) VCC = Max, OC = 4.5V, Dn, Enable = GND
Note 4: All typicals are at VCC = 5V, TA = 25C. Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Min
Typ (Note 4)
Max -1.5
Units V V
2.4
3.1
0.35
0.5 0.4 0.1 20 -0.4 20 -20
V mA A mA A A mA mA
-50 24
-225 40
3
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DM74LS373 * DM74LS374
DM74LS373 Switching Characteristics
at VCC = 5V and TA = 25C RL = 667 Symbol Parameter From (Input) To (Output) tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Output Enable Time to HIGH Level Output Output Enable Time to LOW Level Output Output Disable Time from HIGH Level Output (Note 6) Output Disable Time from LOW Level Output (Note 6)
Note 6: CL = 5 pF.
CL = 45 pF Min Max 18 18 30 30 28 36 20 25
CL = 150 pF Min Max 26 27 38 36 36 50
Units
Data to Q Data to Q Enable to Q Enable to Q Output Control to Any Q Output Control to Any Q Output Control to Any Q Output Control to Any Q
ns ns ns ns ns ns ns ns
DM74LS374 Recommended Operating Conditions
Symbol VCC VIH VIL IOH IOL tW tSU tH TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Pulse Width (Note 8) Clock HIGH Clock LOW 15 15 20 1 0 70 Parameter Min 4.75 2 0.8 Nom 5 Max 5.25 Units V V V mA mA ns ns ns
-2.6
24
Data Setup Time (Note 7) (Note 8) Data Hold Time (Note 7) (Note 8) Free Air Operating Temperature
C
Note 7: The symbol () indicates the rising edge of the clock pulse is used for reference. Note 8: TA = 25C and V CC = 5V.
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DM74LS373 * DM74LS374
DM74LS374 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II IIH IIL IOZH IOZL IOS ICC Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Off-State Output Current with HIGH Level Output Voltage Applied Off-State Output Current with LOW Level Output Voltage Applied Short Circuit Output Current Supply Current Conditions VCC = Min, II = -18 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIL = Max, VIH = Min IOL = 12 mA, VCC = Min VCC = Max, VI = 7V VCC = Max, VI = 2.7V VCC = Max, VI = 0.4V VCC = Max, VO = 2.7V VIH = Min, VIL = Max VCC = Max, VO = 0.4V VIH = Min, VIL = Max VCC = Max (Note 10) VCC = Max, Dn = GND, OC = 4.5V -50 27 2.4 3.1 0.35 0.25 0.5 0.4 0.1 20 -0.4 20 -20 -225 45 mA A mA A A mA mA Min Typ (Note 9) Max -1.5 Units V V
V
Note 9: All typicals are at VCC = 5V, TA = 25C. Note 10: Not more than one output should be shorted at a time, and the duration should not exceed one second.
DM74LS374 Switching Characteristics
at VCC = 5V and TA = 25C RL = 667 Symbol Parameter CL = 45 pF Min fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ Maximum Clock Frequency Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Output Enable Time to HIGH Level Output Output Enable Time to LOW Level Output Output Disable Time from HIGH Level Output (Note 11) Output Disable Time from LOW Level Output (Note 11)
Note 11: CL = 5 pF.
CL = 150 pF Min 20 Max
Units
Max
35 28 28 28 28 20 25
MHz 32 38 44 44 ns ns ns ns ns ns
5
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DM74LS373 * DM74LS374
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
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DM74LS373 * DM74LS374
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
7
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DM74LS373 * DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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